The present invention relates to a nonvolatile semiconductor memory device and more particularly to a highly reliable nonvolatile semiconductor memory device that enables low voltage fast programming.
MNOS (Metal-Nitride-Oxide-Semiconductor) memories and MONOS (Metal-Oxide-Nitride-Oxide-Semiconductor) memories are typical examples of nonvolatile memories (nonvolatile semiconductor memory devices) having storage nodes formed with insulator films. An MNOS memory is structured as a laminated layer comprising a conductive gate electrode layer (M), a silicon nitride film (N), a silicon oxide film (O), and a semiconductor substrate (S). An MNOS memory is structured as a laminated layer comprising a conductive gate electrode layer (M), a silicon oxide film (O), a silicon nitride film (N), a silicon oxide film (O) and a semiconductor substrate (S). In each of those MNOS and MONOS memories, carrier electrons are injected/ejected in/from a silicon nitride film provided with a charge trapping function to store/erase information therein/therefrom.
The structures of the above-described nonvolatile memories and the programming methods for them are disclosed in the patent document 1 (the official gazette of JP-A No. 102466/2001 (corresponding to U.S. Pat. No. 6,255,166)), the patent document 2 (the official gazette of JP-A No. 148434/2001 (corresponding to U.S. Pat. No. 6,388,293)), and the patent document 3 (corresponding to the official gazette of U.S. Pat. No. 5,969,383)
Hereunder, a brief description will be made for both structure and operation of a memory cell of the type disclosed in the patent document 1 (the official gazette of JP-A No. 102466/2001 (corresponding U.S. Pat. No. 6,255,166) and the patent document 2 (the official gazette of JP-A No. 148434/2001) with reference to FIG. 7.
This nonvolatile memory cell is configured by two MOS transistors: a memory MOS transistor used as a storage block and a select MOS transistor used to select the memory block to read information therefrom. The select MOS transistor diffusion layer (source region) 607B is connected to a common line while the select gate electrode 603 is connected to a select-word line. On the other hand, the memory MOS transistor diffusion layer (drain region) 607A is connected to a bit line while the memory gate electrode 605 is connected to a memory word line.
The memory MOS transistor gate capacitor insulator film 604 is formed with a three-layer film, for example, comprising a silicon oxide film (the first layer film) 604a, a silicon nitride film (the second layer film) 604b, and a silicon oxide film (the third layer) 604c formed sequentially on the surface of the silicon substrate 661. Each film thickness is as follows; the first layer 604a is about 3 to 4 nm, the second layer 604b is 10 nm and under, and the third layer 604c is about 2 to 4 nm.
The silicon nitride film formed as the second layer 604b of the memory MOS transistor is actually a charge trapping insulator film (layer) provided with a charge, trapping function. The silicon nitride film traps carrier electrons on the trapping levels formed in the silicone nitride film and at each interface between the silicone nitride film and its upper film and between the silicon nitride film and its lower film. The charge trapping film may be any of a silicon nitride film, a silicon oxynitride film, a tantalum oxide film, etc. The first layer 604a and the third layer 604c are actually potential barrier films, for example, silicon oxide films and/or silicon oxynitride films.
To write information in this nonvolatile memory cell, a predetermined voltage is applied to the diffusion layer (source region) 607B and the gate electrode 603 of the select MOS transistor to turn on the select MOS transistor and a predetermined voltage is applied to the diffusion layer (drain region) 607A and the gate electrode 605 of the memory MOS transistor. At this time, some of the carrier electrons existing on the surface of the silicon substrate are injected into the gate capacitor insulator 604 due to the gate electrical field of the memory MOS transistor. The injected carrier electrons pass through the potential barrier of the silicon oxide film 604a (the first layer) to be trapped in the silicon nitride film (the second layer).
Information is erased from the nonvolatile memory cell in two ways. In one way, carrier electrons are ejected from the silicon nitride film 604b formed as a charge trapping film of the memory MOS transistor towards the silicon substrate 601 through the silicon oxide film 604a formed as a potential barrier film formed beneath the film 604b. In the other way, carrier electrons are ejected to the gate electrode 605 of the memory MOS transistor through the silicon oxide film 604c formed as the third layer. Both of the methods apply a voltage to the gate electrode 605 of the memory MOS transistor to eject the carrier electrons from the silicon nitride film 604b to erase information from the nonvolatile memory cell. The latter method can erase information from the nonvolatile memory cell with use of the same polarity as that used in the write operation has; an advantage that the circuit configuration is simplified; thereby the chip area is reduced.
To read information from the nonvolatile memory cell, it is checked first whether or not a predetermined current flows in the select MOS transistor according to the state of the threshold voltage of the memory MOS transistor when the select MOS transistor is turned on. Stored information is read from the memory cell when the current flows in the transistor.
Next, a brief description will be made for both structure and operation of a memory cell of the type disclosed in the patent document 3 (the official gazette of U.S. Pat. No. 5,969,383) with reference to FIG. 8.
This nonvolatile memory cell is also configured by two MOS transistors; a memory MOS transistor that forms a storage block and a select MOS transistor used to select the memory block to read information therefrom. The select MOS transistor diffusion layer (source region) 707B is connected to a common line while the, select gate electrode 703 is connected to a select-word line. On the other hand, the memory MOS transistor diffusion layer (drain region) 707A is connected to a bit line while the memory gate; electrode 705 is connected to a memory word line.
The memory MOS transistor gate capacitor insulator film 704 is formed as a three-layer film. For example, it consists of a silicon oxide film (the first layer film) 704a, a silicon nitride film (the second layer film) 704b, and a silicon oxide film (the third layer film) 704c formed sequentially on the surface of a silicon substrate 701. Each film thickness is as follows; the first layer 704a is about 5 to 15 nm, the second layer 704b is about 5 to 15 nm, and the third layer film 704c is about 5 to 15 nm. Reference numeral 709 denotes an insulator film.
To write information in this nonvolatile memory cell, a predetermined voltage is applied to the diffusion layer (source region) 707B and the gate electrode 703 of the select MOS transistor to turn on the select MOS transistor and a predetermined voltage is applied to the diffusion layer (drain region) 707A and the gate electrode 705 of the memory MOS transistor respectively. At this time, for example, 0 V is applied to the source region 707B, 1 to 2 V is applied to the gate electrode of the select MOS transistor, 3 to 5 V is applied to the drain region 707A, and 8 to 10 V is applied to the gate electrode 703 of the memory MOS transistor to inject electrons into the silicon nitride film 704b that is part of the gate capacitor insulator.
To erase information from the nonvolatile memory cell, a negative bias is applied to the memory gate electrode 705 and a positive bias to the diffusion layer 707A of the memory MOS transistor respectively to inject hot hales into the charge trapping film by means of band-to-band tunneling. For example, 5 to 7 V is applied to the drain region 707A, xe2x88x929 to xe2x88x921 V is applied to the gate electrode of the memory MOS transistor, and 0 V is applied to the gate electrode 703 of the select MOS transistor respectively or the gate electrode 703 is opened.
To read information from the nonvolatile memory cell, it is checked first whether or not a predetermined current flows in the select MOS transistor according to the state of the threshold voltage of the memory MOS transistor when the select MOS transistor is turned on. Stored information is read from the memory cell when the current flows in the transistor.
The inventor and et al of the present invention have been involved in the research and development of nonvolatile semiconductor memory devices and examined various items for enhancing the performance of the devices.
For example, the inventor et al of the present invention have examined methods for speeding up writing and erasing, methods for suppressing degradation of the transcondactance Gm when in writing and erasing, methods for realizing device structures for improving the charge retention characteristics, and methods for realizing fast writing and erasing.
And, as a result of such examinations to be described later in detail, the inventor et al of the present invention have found that writing and erasing are speeded up and the charge retention characteristics are improved with use of a silicon oxynitride film as a charge trapping insulator film.
The silicon oxynitride film characteristics have not been examined in detail yet in the prior art, although the patent document 1, etc. describe that a silicon oxide film, tantalum oxide film, or silicon oxynitride film of which oxide content is less than the first and third layers is used as the second layer provided with a charge trapping function.
Furthermore, the inventor et al of the present invention forwarded the examination and found that the use of a silicon oxynitride film as a charge trapping insulator film further improves the above characteristics while the transcondactance Gm is degraded. The degradation of this transcondactance GM will be described later in detail.
Under such circumstances, it is the present invention may improve the performance of the nonvolatile semiconductor memory device.
More particularly, the present invention improves the charge retention characteristics, suppress degradation of the transcondactance Gm, and speeds up the operation of the nonvolatile memory.
These together with other features of the present invention will become more apparent in the detailed description which follows and the accompanying drawings.
Typical aspects of the present invention, which are included in those disclosed in this specification, will be summarized as follows.
According to an aspect of the present invention, the nonvolatile semiconductor memory device comprises (a) first and second semiconductor regions formed in a semiconductor substrate, (b) first and second conductors formed on the semiconductor substrate between the first and second semiconductor regions, (c) a first insulator film formed between the first conductor and the semiconductor substrate, and (d) a second insulator film formed between the second conductor and the semiconductor substrate, (e) wherein the second insulator film consists of a potential barrier film formed on the semiconductor substrate and a silicon oxynitride film formed on the potential barrier film. The second conductor is positioned on the silicon oxynitride film.
According to another aspect of the present invention, the nonvolatile semiconductor memory device comprises (a) first and second semiconductor regions formed in a semiconductor substrate, (b) first and second conductors formed on the semiconductor substrate between the first and second semiconductor regions, (c) a first insulator film formed between the first conductor and the semiconductor substrate, and (d) a second insulator film formed between the second conductor and the semiconductor substrate, (e) wherein the second insulator film consists of a potential barrier film formed on the semiconductor substrate and a charge trapping film, (f) wherein the charge trapping film consists of a silicon oxynitride film and a third insulator film in which the sum of an energy between the vacuum level and the film conductor and the band gap of the film is smaller than that of the silicon oxynitride film, and the product of the charge trap density and the film thickness of the silicon oxynitride film is larger than that of the third insulator film.
According to still another aspect of the present invention, the nonvolatile semiconductor memory device comprises (a) first and second semiconductor regions formed in a semiconductor substrate, (b) first and second conductors formed on the semiconductor substrate between the first and second semiconductor regions, (c) a first insulator film formed between the first conductor and the semiconductor substrate, and (d) a second insulator film formed between the second conductor and the semiconductor substrate, (e) wherein the second insulator film consists of a potential barrier film formed on the semiconductor substrate and a silicon oxynitride film formed on the potential barrier film, (f) wherein the silicon oxynitride film has a charge trapping function and electrons trapped in the silicon oxynitride film are erased by holes injected from the semiconductor substrate side.